M68ICS08GR datasheet(211/408 Pages) FREESCALE

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Input/Output Ports (I/O)

Port A

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Input/Output Ports (I/O)

211

Figure 16-4. Port A I/O Circuit

When bit DDRAx is a logic 1, reading address $0000 reads the PTAx

data latch. When bit DDRAx is a logic 0, reading address $0000 reads

the voltage level on the pin. The data latch can always be written,

regardless of the state of its data direction bit. Table 16-2 summarizes

the operation of the port A pins.

READ DDRA ($0004)

WRITE DDRA ($0004)

RESET

WRITE PTA ($0000)

READ PTA ($0000)

PTAx

DDRAx

PTAx

VDD

PTAPUEx

INTERNAL

PULLUP

DEVICE

Table 16-2. Port A Pin Functions

PTAPUE Bit

DDRA Bit

PTA Bit

I/O Pin Mode

Accesses to DDRA

Accesses to PTA

Read/Write

Read

Write

X(1)

Input, VDD

(4)

DDRA3–DDRA0

PTA3–PTA0(3

)

Input, Hi-Z(2)

DDRA3–DDRA0

PTA3–PTA0(3

)

Output

DDRA3–DDRA0

PTA3–PTA0

NOTES:

1. X = Don’t care

2. Hi-Z = High impedance

3. Writing affects data register, but does not affect input.

4. I/O pin pulled up to VDD by internal pullup device

Freescale Semiconductor, Inc.

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