M68ICS08GR datasheet(214/408 Pages) FREESCALE

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Input/Output Ports (I/O)

Technical Data

MC68HC908GR8 — Rev 4.0

214

Input/Output Ports (I/O)

MOTOROLA

16.4.2 Data Direction Register B

Data direction register B (DDRB) determines whether each port B pin is

an input or an output. Writing a logic 1 to a DDRB bit enables the output

buffer for the corresponding port B pin; a logic 0 disables the output

buffer.

DDRB5–DDRB0 — Data Direction Register B Bits

These read/write bits control port B data direction. Reset clears

DDRB5–DDRB0], configuring all port B pins as inputs.

1 = Corresponding port B pin configured as output

0 = Corresponding port B pin configured as input

NOTE:

Avoid glitches on port B pins by writing to the port B data register before

changing data direction register B bits from 0 to 1.

NOTE:

For those devices packaged in a 28-pin DIP and SOIC package, PTB5,4

are not connected. Set DDRB5,4 to a 1 to configure PTB5,4 as outputs.

Figure 16-8 shows the port B I/O logic.

Address:

$0005

Bit 7

654321

Bit 0

Read:

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Write:

Reset:

00000000

Figure 16-7. Data Direction Register B (DDRB)

Freescale Semiconductor, Inc.

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