IO96NDB2V1 datasheet(163/242 Pages) MICROSEMI

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ProASIC3L Low Power Flash FPGAs

Revision 13

2-147

Table 2-219 • FIFO – Applies to 1.2 V DC Core Voltage

Worst Commercial-Case Conditions: TJ = 70°C, VCC = 1.14 V

Parameter

Description

–1

Std.

Units

tENS

REN, WEN Setup Time

1.84

2.16

tENH

REN, WEN Hold Time

0.02

0.03

tBKS

BLK Setup Time

0.40

0.47

tBKH

BLK Hold Time

0.00

tDS

Input Data (WD) Setup Time

0.24

0.29

tDH

Input Data (WD) Hold Time

0.00

tCKQ1

Clock High to New Data Valid on RD (flow-through)

3.14

3.69

tCKQ2

Clock High to New Data Valid on RD (pipelined)

1.19

1.40

tRCKEF

RCLK High to Empty Flag Valid

2.29

2.69

tWCKFF

WCLK High to Full Flag Valid

2.18

2.56

tCKAF

Clock High to Almost Empty/Full Flag Valid

8.25

9.70

tRSTFG

RESET Low to Empty/Full Flag Valid

2.26

2.65

tRSTAF

RESET Low to Almost Empty/Full Flag Valid

8.17

9.60

tRSTBQ

RESET Low to Data Out Low on RD (flow-through)

1.23

1.45

RESET Low to Data Out Low on RD (pipelined)

1.23

1.45

tREMRSTB

RESET Removal

0.38

0.45

tRECRSTB

RESET Recovery

2.00

2.35

tMPWRSTB

RESET Minimum Pulse Width

0.63

0.72

tCYC

Clock Cycle Time

5.75

6.61

FMAX

Maximum Frequency for FIFO

174

151

MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for

derating values.

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