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IO96NDB2V1 Datasheet(PDF) 165 Page - Microsemi Corporation |
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IO96NDB2V1 Datasheet(HTML) 165 Page - Microsemi Corporation |
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165 / 242 page  ProASIC3L Low Power Flash FPGAs Revision 13 2-149 JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O Characteristics" section on page 2-18 for more details. Timing Characteristics Table 2-222 • JTAG 1532 – Applies to 1.5 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V Parameter Description –1 Std. Units tDISU Test Data Input Setup Time 0.57 0.67 ns tDIHD Test Data Input Hold Time 1.13 1.33 ns tTMSSU Test Mode Select Setup Time 0.57 0.67 ns tTMDHD Test Mode Select Hold Time 1.13 1.33 ns tTCK2Q Clock to Q (data out) 5.67 6.67 ns tRSTB2Q Reset to Q (data out) 22.67 26.67 ns FTCKMAX TCK Maximum Frequency 24.00 21.00 MHz tTRSTREM ResetB Removal Time 0.00 0.00 ns tTRSTREC ResetB Recovery Time 0.23 0.27 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-223 • JTAG 1532 – Applies to 1.2 V DC Core Voltage Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V Parameter Description –1 Std. Units tDISU Test Data Input Setup Time 0.75 0.88 ns tDIHD Test Data Input Hold Time 1.50 1.76 ns tTMSSU Test Mode Select Setup Time 0.75 0.88 ns tTMDHD Test Mode Select Hold Time 1.50 1.76 ns tTCK2Q Clock to Q (data out) 6.00 7.06 ns tRSTB2Q Reset to Q (data out) 25.00 29.41 ns FTCKMAX TCK Maximum Frequency 20.00 17.00 MHz tTRSTREM ResetB Removal Time 0.45 0.53 ns tTRSTREC ResetB Recovery Time 0.00 0.00 ns tTRSTMPW ResetB Minimum Pulse TBD TBD ns Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. |
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