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AN2941 Datasheet(PDF) 19 Page - STMicroelectronics |
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AN2941 Datasheet(HTML) 19 Page - STMicroelectronics |
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19 / 37 page ![]() AN2941 Functional check Doc ID 15447 Rev 4 19/37 In Figure 18 we can see that, in this case, the IC supply voltage drops to the UVLO threshold (10 V) causing controller turn-off before the SS pin signal attains the disable threshold (5 V). This happens because the transformer leakage inductance is very low and as soon as the output voltage drops, the auxiliary voltage drops immediately as well. Furthermore from the graph we can note that, during the SS voltage ramp-up, the transferred power is limited. Overvoltage and open loop protection The EVL6566A-75WES4 board implements two different open loop protections, one for each stage. The PFC controller L6563S is equipped with an OVP monitoring the output voltage by the PFC_OK (#7) pin with a resistor divider (R3, R5, R11 high, R10 and R19 low). This divider is selected so that the voltage at the pin reaches 2.5 V if the output voltage exceeds a preset value (455 V in this case). When this function is triggered, the gate drive activity is immediately stopped and it restarts as the voltage on the pin falls below 2.4 V. This function protects the bulk capacitor from voltage surges caused by abrupt load/line changes or startup overshoot. Because, in this case no failure occurred, the controller restarts as the output voltage falls below the overvoltage threshold. However, if the voltage on pin INV falls below 1.66 V (typ.) a feedback failure is assumed. In this case the device is latched off. Normal operation can be resumed only by cycling Vcc, bringing its value lower than 6 V, before moving up to turn-on threshold. At the same time the pin PWM_LATCH (pin #8) is asserted high. This pin is an open source output intended for tripping a latched shutdown function of the PWM controller IC in the cascaded DC-DC converter, so that the entire unit is latched off. On this board the PWM_LATCH is connected to the DIS pin of the L6566A. Figure 17. Short-circuit at full load and 230 Vac - 50 Hz Figure 18. Short-circuit details at full load and 230 Vac - 50 Hz CH1: Gate voltage CH2: Vcc CH3: SS pin voltage CH4: Output current CH1: Drain voltage CH2:Vcc CH3: SS pin voltage CH4: Output current |
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