AN4460 datasheet(16/54 Pages) STMICROELECTRONICS

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SMED implementation

AN4460

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DocID026129 Rev 1

SMED implementation

This section describes how the FOT (fixed off-time) principle is implemented in the SMED

(state machine event driven). Each SMED generates the correct PWM signals and the

SMED state evolution depends on both external events and internal timers.

Note:

Please refer to the STLUX385A product documentation for a detailed explanation of the

SMED technology.

The SMED is responsible for the generation of the PWM necessary to maintain the IAVG

current through the LEDs. When the SMED is triggering the PWM output, the LEDs are ON.

Digital dimming is achieved by applying a duty cycle to the LEDs. The software controls the

duty cycle (referred as dimming in this document) by suspending and restoring the SMED's

PWM generation. When the SMED stops triggering the PWM line, the LEDs are OFF.

Note that the dimming frequency is much lower (~200 Hz) than the PWM frequency used for

current control (70 kHz - 400 kHz).

4.1

SMED input matrix

Each SMED has three associated signals. Only two inputs are used in the FOT principle

described in this AN. The inputs have been logically mapped to represent:



SMED_in(0) - digital input: senses the inductor null current (currently not used).



SMED_in(1) - comparator input: detects when the current has reached the DAC value.



SMED_in(2) - software input: starts and stops the SMED. Used for dimming control.

Table 2 summarizes the input and event relationship:

Option:



SMED 4 PWM output is optional.



SMED 5 PWM output is filtered and connected to CPM3. SMED5 may be optionally

used to generate a reference signal for the CPM(3) input. CPM3 can be used to sense

and detect the top-current event for LED channel 0 and increase the string average

current granularity. The possible current steps are equal to 5 mA (typical). This option is

not used in the current firmware version.

Table 2. SMED input association

LED CH

SMED_in(0)

SMED_in(1)

SMED_in(2)

SMED 0

DIGIN 2

DAC-CPP 3

SW 0

SMED 1

DIGIN 1

DAC-CPP 2

SW 1

SMED 2

DIGIN 4

DAC-CPP 0

SW 2

SMED 3

DIGIN 3

DAC-CPP 1

SW 3

SMED 4

Not used

DIGIN 0

SW 4

SMED 5

Not used

SW 5

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