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AN4192 Datasheet(PDF) 36 Page - STMicroelectronics |
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AN4192 Datasheet(HTML) 36 Page - STMicroelectronics |
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36 / 47 page ![]() Low-side FET selection AN4192 36/47 Doc ID 023820 Rev 1 Figure 44. 1 x LS vs. 2 x LS (LS G-S ringing improvement) The conspicuous reduction of the LS gate-source bouncing (especially for the high frequency oscillation after the first spike) provided by the increased COSS is obtained also using a bigger die size LS device, as shown in Figure 45 (light green trace: LS1, dark green trace: LS2). Figure 45. LS gate-source bouncing reduction for bigger die size LS FETs AM16487V1 AM16488V1 |
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