AN4192 datasheet(38/47 Pages) STMICROELECTRONICS

38 / 47 page

Low-side FET selection

AN4192

38/47

Doc ID 023820 Rev 1

Figure 47.

Phase node waveform and fRING evaluation

Equation 9

The snubber capacitor value is a trade-off between the over-damping effect (reduction of the

number of oscillations) (high CSNUB) and limited energy losses (low CSNUB). Typically, the

snubber network constant time (

τ SNUB) is chosen as:

Equation 10

The correct fine tuning of the snubber components, together with a suitable selection of the

external gate resistors, allows a sensible reduction of the phase node overshoot. For

example, let's consider a single-phase synchronous buck converter (VIN = 12 V, VOUT = 1.25

V, fSW = 270 kHz, 1 x HS, 1 x LS, IOUT = 20 A, with the following original configuration:

CSNUB = 6.8 nF, RSNUB = 1.8 Ω, RG,HS(EXT) = 0 Ω, RG,LS(EXT) = 0 Ω) . Moreover, a very low

QG,SW HS FET is used to maximize the switching speed and emphasize the phase node

ringing issue. In Figure 48, the waveforms for the original configuration are shown: the

maximum phase node spike is 33.6 V.

AM16490V1

stray

RING

OSS

⋅⋅

--------------------------------------------------------

SNUB

RING

--------------

⋅

AN4192 Datasheet(PDF) 38 Page - STMicroelectronics