DocID17496 Rev 7

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AN3216

Clocks

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3.4

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is

enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.

If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled

and an interrupt is generated to inform the software about the failure (clock security system

interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the

Cortex™-M3 NMI (non-maskable interrupt) exception vector.

If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is

used as the PLL input clock, and the PLL clock is used as the system clock), a detected

failure causes the system clock to switch to the MSI oscillator and the external HSE

oscillator to be disabled. If the HSE oscillator clock is the clock entry of the PLL used as the

system clock when the failure occurs, the PLL is also disabled.

For details, see the STM32L1xxx reference manual (RM0038).