AN4031 datasheet(6/36 Pages) STMICROELECTRONICS

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DMA controller description

AN4031

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DMA controller description

The DMA is an AMBA advanced high-performance bus (AHB) module that features three

AHB ports: a slave port for DMA programming and two master ports (peripheral and

memory ports) that allow the DMA to initiate data transfers between different slave modules.

The DMA allows data transfers to take place in the background, without the intervention of

the Cortex-Mx processor. During this operation, the main processor can execute other tasks

and it is only interrupted when a whole data block is available for processing.

Large amounts of data can be transferred with no major impact on the system performance.

The DMA is mainly used to implement central data buffer storage (usually in the system

SRAM) for different peripheral modules. This solution is less expensive in terms of silicon

and power consumption compared to a distributed solution where each peripheral needs to

implement it own local data storage.

The STM32F2/F4 DMA controller takes full advantage of the Cortex-Mx Harvard

architecture and the multi-layer bus system in order to ensure very low latency both for DMA

transfers and for CPU execution/interrupt event detection/service.

1.1

DMA transfer properties

A DMA transfer is characterized by the following properties:

•

DMA stream/channel

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Stream priority

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Source and destination addresses

•

Transfer mode

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Transfer size (only when DMA is the flow controller)

•

Source/destination address incrementing or non-incrementing

•

Source and destination data width

•

Transfer type

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FIFO mode

•

Source/destination burst size

•

Double-buffer mode

•

Flow control

STM32F2/F4 devices embed two DMA controllers, and each DMA has two port, one

peripheral port and one memory port, which can work simultaneously.

Figure 1 shows the DMA block diagram.

AN4031 Datasheet(PDF) 6 Page - STMicroelectronics

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