AN4031 datasheet(19/36 Pages) STMICROELECTRONICS

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AN4031

System performance considerations

2.1.2

Round-robin priority scheme

A round-robin priority scheme is implemented at bus matrix level in order to ensure that

each master can access any slave with very low latency:

•

Round-robin arbitration policy allows a fair distribution of bus bandwidth.

•

Maximum latency is bounded.

•

Round-robin quantum is 1x transfer.

Bus matrix arbiters intervene to solve access conflicts when several AHB masters try to

access the same AHB slave simultaneously.

In the following example (Figure 8), both the CPU and DMA1 try to access SRAM1 to read

data.

Figure 8. CPU and DMA1 request an access to SRAM1

In case of bus access concurrency as in the above example, a bus matrix arbitration is

required. The round-robin policy is then applied in order to solve the issue: if the last master

which wan the bus was the CPU, during the next access DMA1 wins the bus and accesses

SRAM1 first. The CPU has then the rights to access SRAM1.

This proves that the transfer latency associated to one master depends on the number of

other pending master requests to access the same AHB slave. In the following example

(Figure 9), five masters try to access simultaneously SRAM1.

AN4031 Datasheet(PDF) 19 Page - STMicroelectronics