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AN4031 Datasheet(PDF) 12 Page - STMicroelectronics

Part # AN4031
Description  Using the STM32F2 and STM32F4 DMA controller
PDF  36 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN4031 Datasheet(HTML) 12 Page - STMicroelectronics

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DMA controller description
AN4031
12/36
DocID022648 Rev 1
The DMA FIFOs implemented on STM32F2/F4 devices help to:
•
reduce SRAM access and so give more time for the other masters to access the bus
matrix without additional concurrency,
•
allow software to do burst transactions which optimize the transfer bandwidth,
•
allow packing/unpacking data to adapt source and destination data width with no extra
DMA access.
Figure 4. FIFO structure
Source: byte
4 words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4
1/2
3/4
Full
Empty
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B 11
B12
B13
B14
B15
Destination: word
Source: byte
Destination: half-word
4 words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4
1/2
3/4
Full
Empty
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B 11
B12
B13
B14
B15
W0
W1
W2
W3
H0
H1
H2
H3
H4
H5
H6
H7
Source: half-word
Destination: word
4 words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4
1/2
3/4
Full
Empty
H0
W0
W1
W2
W3
H1
H2
H3
H4
H5
H6
H7
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
H7 H6 H5 H4 H3 H2 H1 H0
H7, H6, H5, H4, H3, H2, H1, H0
W3, W2, W1, W0
W3, W2, W1, W0
Source: half-word
4-words
byte lane 0
byte lane 1
byte lane 2
byte lane 3
1/4
1/2
3/4
Full
Empty
Destination: byte
H7 H6 H5 H4 H3 H2 H1 H0
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B 11
B12
B13
B14
B15
H0
H1
H2
H3
H4
H5
H6
H7
B15 B14 B13 B12 B11 B10 B9 B8
B7 B6 B5 B4 B3 B2 B1 B0
ai15951



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