AN4031 datasheet(8/36 Pages) STMICROELECTRONICS

8 / 36 page

DMA controller description

AN4031

8/36

DocID022648 Rev 1

Figure 2. Channel selection

Note:

Only one channel/request can be active at the same time in a stream.

More than one enabled DMA stream must not serve the same peripheral request.

Table 2 and Table 3 show the possible configurations of DMA streams/channels versus

peripheral requests for all the supported products except STM32F401, which is described in

Table 4 and Table 5.

REQ_STREAMx

REQ_STRx_CH7

REQ_STRx_CH6

REQ_STRx_CH5

REQ_STRx_CH4

REQ_STRx_CH3

REQ_STRx_CH2

REQ_STRx_CH1

REQ_STRx_CH0

CHSEL[2:0]

DMA_SxCR

ai15947

Table 2. DMA1 request mapping

Peripheral

requests

Stream 0

Stream 1

Stream 2

Stream 3

Stream 4

Stream 5

Stream 6

Stream 7

Channel 0

SPI3_RX

SPI2_RX

SPI2_TX

SPI3_TX

Channel 1

I2C1_RX

TIM7_UP

I2C1_RX

I2C1_TX

Channel 2

TIM4_CH1

I2S3_EXT_

TIM4_CH2

I2S2_EXT_

I2S3_EXT_

TIM4_UP

TIM4_CH3

Channel 3

I2S3_EXT_

TIM2_UP

TIM2_CH3

I2C3_RX

I2S2_EXT_

I2C3_TX

TIM2_CH1

TIM2_CH2

TIM2_CH4

TIM2_UP

TIM2_CH4

Channel 4

UART5_RX

USART3_RX

UART4_RX

USART3_TX

UART4_TX

USART2_RX

USART2_TX

UART5_TX

Channel 5

UART8_TX(1)

UART7_TX(1)

TIM3_CH4

TIM3_UP

UART7_RX(1)

TIM3_CH1

TIM3_TRIG

TIM3_CH2

UART8_RX(1)

TIM3_CH3

Channel 6

TIM5_CH3

TIM5_UP

TIM5_CH4

TIM5_TRIG

TIM5_CH1

TIM5_CH4

TIM5_TRIG

TIM5_CH2

TIM5_UP

Channel 7

TIM6_UP

I2C2_RX

USART3_TX

DAC1

DAC2

I2C2_TX

1. These requests are available on STM32F42xx and STM32F43xx only.

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