AN4031 datasheet(27/36 Pages) STMICROELECTRONICS

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AN4031

How to predict DMA latencies

When designing a firmware application based on a microcontroller, the user must ensure

that no underrun/overrun can occur, and that’s why knowing the exact DMA latency for each

transfer is mandatory to check if the internal system can sustain the total data bandwidth

required for the application.

3.1

DMA transfer time

3.1.1

Default DMA transfer timing

As described in Section 2.2.2, to perform a DMA transfer from peripheral to memory, two

bus accesses are required:

•

One access over peripheral port triggered by peripheral request, which needs:

–

DMA peripheral port request arbitration

–

Peripheral address computation

–

Reading data from the peripheral to DMA FIFO (DMA source)

•

One access over memory port which can be triggered by the FIFO threshold (when

FIFO mode is used) or immediately after peripheral read (when Direct mode is used),

which needs:

–

DMA memory port request arbitration

–

Memory address computation

–

Writing loaded data in SRAM (DMA destination)

When transferring data from memory to peripheral, two accesses are also required as

described in Section 2.2.2:

•

First access: DMA anticipates peripheral access and reads data from memory and

stores it in FIFO to ensure an immediate data transfer as soon as DMA peripheral

request is triggered. This operation needs:

–

DMA memory port request arbitration

–

Memory address computation

–

Reading data from memory to DMA FIFO (DMA source)

•

Second access: when peripheral request is triggered, a transfer is generated on DMA

peripheral port. This operation needs:

–

DMA peripheral port request arbitration

–

Peripheral address computation

–

Writing loaded data at peripheral address (DMA destination)

As a general rule, the total transfer time by DMA stream TS is equal to:

TS = TSP (peripheral access/transfer time) + TSM (memory access/transfer time)

With:

TSP is the total timing for DMA peripheral port access and transfer which is equal to:

TSP = tPA+ tPAC + tBMA + tEDT + tBS

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