AN4031 datasheet(18/36 Pages) STMICROELECTRONICS

18 / 36 page

System performance considerations

AN4031

18/36

DocID022648 Rev 1

Figure 7. System architecture

2.1

Multi-layer bus matrix

The multi-layer bus matrix allows masters to perform data transfers concurrently as long as

they are addressing different slave modules. On top of the Cortex-Mx Harvard architecture

and dual AHB port DMAs, this structure enhances data transfer parallelism, thus

contributing to reduce the execution time, and optimizing the DMA efficiency and power

consumption.

2.1.1

Definitions

•

AHB master: a bus master is able to initiate read and write operations. Only one master

can win bus ownership at a defined time period.

•

AHB slave: a bus slave response to master read or write operations. The bus slave

signals back to master success, failure or waiting states.

•

AHB arbiter: a bus arbiter insures that only one master can initiate a read or write

operation at one time.

•

AHB bus matrix: a multi-layer AHB bus matrix that interconnects AHB masters to AHB

slaves with dedicated AHB arbiter for each layer. The arbitration uses a round-robin

algorithm.

AN4031 Datasheet(PDF) 18 Page - STMicroelectronics