AN4031 datasheet(17/36 Pages) STMICROELECTRONICS

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AN4031

System performance considerations

STM32F2/F4 devices embed a multi-masters/multi-slaves architecture:

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Eight masters:

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Cortex™-Mx core I-bus

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Cortex™-Mx core D-bus

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Cortex™-Mx core S-bus

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DMA1 memory bus

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DMA2 memory bus

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DMA2 peripheral bus

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Ethernet DMA bus

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USB high-speed DMA bus

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Eight slaves:

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Internal Flash memory ICode bus

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Internal Flash memory DCode bus

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Main internal SRAM1 (112 KB, 64 KB on STM32F401x)

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Auxiliary internal SRAM2 (16 KB) (not available on STM32F401)

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Auxiliary internal SRAM3 (64 KB) available only on STM32F42x/F43x devices

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AHB1 peripherals including AHB-to-APB bridges and APB peripherals

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AHB2 peripherals

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AHB3 peripheral (FMC) (not available on STM32F401)

Masters and slaves are connected via a multi-layer bus matrix ensuring concurrent access

and efficient operation, even when several high-speed peripherals work simultaneously.

This architecture is shown in the next figure for the case of STM32F40x/F41x.

AN4031 Datasheet(PDF) 17 Page - STMicroelectronics

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