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UPD78323LP Datasheet(PDF) 32 Page - NEC |
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UPD78323LP Datasheet(HTML) 32 Page - NEC |
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32 / 86 page  32 µPD78323, 78324 3.6 CLOCK GENERATOR The clock generator generates and controls internal system clocks (CLK) supplied to the CPU. It is configured as shown in Figure 3-1. Figure 3-1. Block Diagram of Clock Generator X1 X2 STOP Mode fXX or fX 1/2 fCLK Internal System Clock (CLK) Divider System Clock Generator Remarks 1. fXX : Crystal oscillator frequency 2. fX : External clock frequency 3. fCLK : Internal system clock frequency The system clock oscillator oscillates by a crystal resonator connected to X1 and X2 pins. It stops oscillating when set to the standby mode (STOP). External clocks can be input to the system clock oscillator. In such cases, input a clock signal to the X1 pin and input the reverse phase of the clock signal to the X2 pin. The X2 pin can also be left open. Caution When using external clocks, do not set the STBC STP bit. The divider generates internal system clocks (fCLK) by dividing a system clock oscillator output (fxx for crystal oscillation and fx for external clocks) into two parts. |
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