UPD78323LP datasheet(22/86 Pages) NEC

22 / 86 page

µPD78323, 78324

(4)

CPU control word (CCW)

This is an 8-bit register consisting of CPU control related flags. It is mapped in the special function register area and can

be controlled by the software.

All bits are reset to 0 by RESET input.

Figure 2-4. CCW Format

• Table position flag (TPF)

This flag is used to specify the interrupt vector table area and the memory area used as CALLT instruction table area.

As TPF has been reset to 0 after application of RESET input, the 0000H to 007FH address is used as each table area.

The 8002H to 807FH address of the external memory area in place of 0002H to 007FH address can be used as each table

area by setting TPF to 1 using the software. The vector tables of the BRK instruction, operation code trap interrupt and reset

input are fixed to 003EH, 003CH and 0000H, respectively, and they are not affected by TPF.

2.2.2

General Registers

These are 128-byte registers mapped in the special area (FE80H to FEFFH) of the internal RAM space. They consist

of eight register banks. The general register in the bank consists of sixteen 8-bit registers.

Figure 2-5. General Register Memory Location

54321

0000

TPF

CCW

(FH)

RP7

(EH)

(DH)

RP6

(CH)

(BH)

RP5

(AH)

(9H)

RP4

(8H)

(7H)

RP3

(6H)

(5H)

RP2

(4H)

(3H)

RP1

(2H)

(1H)

RP0

(0H)

R15

R14

R13

R12

R11

R10

70 7

RBNK0

RBNK1

RBNK2

RBNK3

RBNK4

RBNK5

RBNK6

RBNK7

FEFFH

FE80H

8-Bit Processing

16-Bit Processing

UPD78323LP Datasheet(PDF) 22 Page - NEC

UPD78323LP Datasheet(HTML) 22 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL