PIC16LC773-04SLASHSP datasheet(27/200 Pages) MICROCHIP

27 / 200 page

PIC16C77X

Advance Information

DS30275A-page 27

3.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the

PICmicro™

Mid-Range

Reference

Manual,

(DS33023).

3.1

PORTA and the TRISA Register

PORTA is a 6-bit wide bi-directional port for the 40/44

pin devices and is 5-bits wide for the 28-pin devices.

PORTA<5> is not on the 28-pin devices. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (=1) will make the corresponding PORTA pin

an input, i.e., put the corresponding output driver in a

hi-impedance mode. Clearing a TRISA bit (=0) will

make the corresponding PORTA pin an output, i.e., put

the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore a write to a port implies that the port pins are

read, this value is modified, and then written to the port

data latch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schmitt Trigger input and an open drain output.

All other RA port pins have TTL input levels and full

CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs

and analog VREF inputs and precision on-board refer-

ences (VRL/VRH). The operation of each pin is

selected by clearing/setting the control bits in the

ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA

pins, even when they are being used as analog inputs.

The user must ensure the bits in the TRISA register are

maintained set when using them as analog inputs.

EXAMPLE 3-1:

INITIALIZING PORTA

BCF

STATUS, RP0

;

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

BSF

STATUS, RP0

; Select Bank 1

MOVLW

0xCF

; Value used to

; initialize data

; direction

MOVWF

TRISA

; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as ’0’.

FIGURE 3-1:

BLOCK DIAGRAM OF

RA3:RA2 PINS

Note:

On a Power-on Reset, these pins are con-

figured as analog inputs and read as '0'.

Data

bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VSS

VDD

I/O pin(1)

Note 1:

I/O pins have protection diodes to VDD and

VSS.

Analog

input

mode

TTL

input

buffer

To A/D Converter

VRH, VRL

VRHOEN, VRLOEN

Sense input for

VRO+, VRO- amplifier

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