PIC16LC773-04SLASHSP datasheet(58/200 Pages) MICROCHIP

58 / 200 page

PIC16C77X

DS30275A-page 58

Advance Information

determine when the transmission/reception has com-

pleted. The SSPBUF must be read and/or written. If the

interrupt method is not going to be used, then software

polling can be done to ensure that a write collision does

not occur. Example 8-1 shows the loading of the

SSPBUF (SSPSR) for data transmission.

EXAMPLE 8-1:

LOADING THE SSPBUF

(SSPSR) REGISTER

The SSPSR is not directly readable or writable, and can

only be accessed by addressing the SSPBUF register.

Additionally, the MSSP status register (SSPSTAT) indi-

cates the various status conditions.

8.1.2

ENABLING SPI I/O

To enable the serial port, MSSP Enable bit, SSPEN

(SSPCON<5>) must be set. To reset or reconfigure SPI

mode, clear bit SSPEN, re-initialize the SSPCON reg-

isters, and then set bit SSPEN. This configures the

SDI, SDO, SCK, and SS pins as serial port pins. For the

pins to behave as the serial port function, some must

have their data direction bits (in the TRIS register)

appropriately programmed. That is:

• SDI is automatically controlled by the SPI module

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

•SS must have TRISA<5> set

Any serial port function that is not desired may be over-

ridden by programming the corresponding data direc-

tion (TRIS) register to the opposite value.

8.1.3

TYPICAL CONNECTION

Figure 8-5 shows a typical connection between two

microcontrollers. The master controller (Processor 1)

initiates the data transfer by sending the SCK signal.

Data is shifted out of both shift registers on their pro-

grammed clock edge, and latched on the opposite edge

of the clock. Both processors should be programmed to

same Clock Polarity (CKP), then both controllers would

send and receive data at the same time. Whether the

data is meaningful (or dummy data) depends on the

application software. This leads to three scenarios for

data transmission:

• Master sends data — Slave sends dummy data

• Master sends data — Slave sends data

• Master sends dummy data — Slave sends data

FIGURE 8-5:

SPI MASTER/SLAVE CONNECTION

BSF

STATUS, RP0

;Specify Bank 1

LOOP BTFSS SSPSTAT, BF

;Has data been

;received

;(transmit

;complete)?

GOTO

LOOP

;No

BCF

STATUS, RP0

;Specify Bank 0

MOVF

SSPBUF, W

;W reg = contents

;of SSPBUF

MOVWF RXDATA

;Save in user RAM

MOVF

TXDATA, W

;W reg = contents

; of TXDATA

MOVWF SSPBUF

;New data to xmit

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

MSb

LSb

SDO

SDI

PROCESSOR 1

SCK

SPI Master SSPM3:SSPM0 = 00xxb

Serial Input Buffer

(SSPBUF)

Shift Register

(SSPSR)

LSb

MSb

SDI

SDO

PROCESSOR 2

SCK

SPI Slave SSPM3:SSPM0 = 010xb

Serial Clock

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