PIC16LC773-04SLASHSP datasheet(89/200 Pages) MICROCHIP

89 / 200 page

PIC16C77X

Advance Information

DS30275A-page 89

8.2.15

CLOCK ARBITRATION

Clock arbitration occurs when the master, during any

receive, transmit, or repeated start/stop condition, de-

asserts the SCL pin (SCL allowed to float high). When

the SCL pin is allowed to float high, the baud rate gen-

erator (BRG) is suspended from counting until the SCL

pin is actually sampled high. When the SCL pin is sam-

pled high, the baud rate generator is reloaded with the

contents of SSPADD<6:0> and begins counting. This

ensures that the SCL high time will always be at least

one BRG rollover count in the event that the clock is

held low by an external device (Figure 8-33).

8.2.16

SLEEP OPERATION

While in sleep mode, the I2C module can receive

addresses or data, and when an address match or

complete byte transfer occurs wake the processor from

sleep ( if the SSP interrupt is enabled).

8.2.17

EFFECTS OF A RESET

A reset disables the SSP module and terminates the

current transfer.

FIGURE 8-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE

SCL

SDA

BRG overflow,

Release SCL,

If SCL = 1 Load BRG with

SSPADD<6:0>, and start count

BRG overflow occurs,

Release SCL, Slave device holds SCL low.

SCL = 1 BRG starts counting

clock high interval.

SCL line sampled once every machine cycle (Tosc • 4).

Hold off BRG until SCL is sampled high.

BRG

to measure high time interval

PIC16LC773-04/SP Datasheet(PDF) 89 Page - Microchip Technology