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PIC16LC773-04/SP Datasheet(PDF) 54 Page - Microchip Technology

Part # PIC16LC773-04/SP
Description  28/40-Pin, 8-Bit CMOS Microcontrollers w/ 12-Bit A/D
PDF  200 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC16LC773-04/SP Datasheet(HTML) 54 Page - Microchip Technology

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PIC16C77X
DS30275A-page 54
Advance Information
© 1999 Microchip Technology Inc.
FIGURE 8-1:
SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 94h)
R/W-0 R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
PS
R/W
UA
BF
R =Readable bit
W =Writable bit
U =Unimplemented bit, read
as ‘0’
- n =Value at POR reset
bit7
bit0
bit 7:
SMP: Sample bit
SPI Master Mode
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave Mode
SMP must be cleared when SPI is used in slave mode
In I2C master or slave mode:
1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz)
0= Slew rate control enabled for high speed mode (400 kHz)
bit 6:
CKE: SPI Clock Edge Select (Figure 8-6, Figure 8-8, and Figure 8-9)
CKP = 0
1 = Data transmitted on rising edge of SCK
0 = Data transmitted on falling edge of SCK
CKP = 1
1 = Data transmitted on falling edge of SCK
0 = Data transmitted on rising edge of SCK
bit 5:
D/A: Data/Address bit (I2C mode only)
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
bit 4:
P: Stop bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET)
0 = Stop bit was not detected last
bit 3:
S: Start bit
(I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared)
1 = Indicates that a start bit has been detected last (this bit is '0' on RESET)
0 = Start bit was not detected last
bit 2:
R/W: Read/Write bit information (I2C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from the
address match to the next start bit, stop bit, or not ACK bit.
In I2C slave mode:
1 = Read
0 = Write
In I2C master mode:
1 = Transmit is in progress
0 = Transmit is not in progress.
Or’ing this bit with SEN, RSEN, PEN, RCEN, or AKEN will indicate if the MSSP is in IDLE mode
bit 1:
UA: Update Address (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0:
BF: Buffer Full Status bit
Receive (SPI and I2C modes)
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (I2C mode only)
1 = Data Transmit in progress (does not include the ACK and stop bits), SSPBUF is full
0 = Data Transmit complete (does not include the ACK and stop bits), SSPBUF is empty



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