PIC16LC773-04SLASHSP datasheet(73/200 Pages) MICROCHIP

73 / 200 page

PIC16C77X

Advance Information

DS30275A-page 73

The MSSP Module shifts in the ACK bit from the

slave device, and writes its value into the

SSPCON2 register ( SSPCON2<6>).

The MSSP module generates an interrupt at the

end of the ninth clock cycle by setting the SSPIF

bit.

The user generates a STOP condition by setting

the STOP enable bit PEN in SSPCON2.

Interrupt is generated once the STOP condition

is complete.

8.2.8

BAUD RATE GENERATOR

In I2C master mode, the reload value for the BRG is

located in the lower 7 bits of the SSPADD register

(Figure 8-18). When the BRG is loaded with this value,

the BRG counts down to 0 and stops until another

reload has taken place. The BRG count is decremented

twice per instruction cycle (TCY) on the Q2 and Q4

clock.

In I2C master mode, the BRG is reloaded automatically.

If Clock Arbitration is taking place for instance, the BRG

will be reloaded when the SCL pin is sampled high

(Figure 8-19).

FIGURE 8-18: BAUD RATE GENERATOR

BLOCK DIAGRAM

FIGURE 8-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION

SSPM3:SSPM0

BRG Down Counter

CLKOUT

Fosc/4

SSPADD<6:0>

SSPM3:SSPM0

SCL

Reload

Control

Reload

SDA

SCL

SCL de-asserted but slave holds

DX-1

BRG

SCL is sampled high, reload takes

place, and BRG starts its count.

03h

02h

01h

00h (hold off)

03h

02h

reload

BRG

value

SCL low (clock arbitration)

SCL allowed to transition high

BRG decrements

(on Q2 and Q4 cycles)

PIC16LC773-04/SP Datasheet(PDF) 73 Page - Microchip Technology

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