XRT72L13 datasheet(12/370 Pages) EXAR

12 / 370 page

XRT72L13

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

REV. P1.0.6

PRELIMINARY

Figure 98. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS

and RxNEG are to be sampled on the falling edge of RxLineClk .................................... 292

4.3.2 The Receive DS3 Framer Block ......................................................................................................... 292

Figure 99. A Simple Illustration of the Receive DS3 Framer Block and the Associated Paths to the

Other Functional Blocks ..................................................................................................... 292

Figure 100. The State Machine Diagram for the "Receive DS3 Framer" block's "Frame Acquisition/

Maintenance" Algorithm ..................................................................................................... 293

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ...................................................... 294

TABLE 31: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE "RX DS3

CONFIGURATION AND STATUS" REGISTER, AND THE RESULTING "FRAMING ACQUISITION CRITERIA ...

294

"RX DS3 CONFIGURATION AND STATUS" REGISTER, (ADDRESS = 0X10) .................................................... 295

TABLE 32: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CON-

FIGURATION AND

STATUS REGISTER, AND THE RESULTING "F-BIT OOF DECLARATION CRITERIA" USED

BY THE

"RECEIVE DS3 FRAMER" BLOCK ................................................................................... 295

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ...................................................... 295

TABLE 33: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE "RX DS3 CON-

FIGURATION AND

STATUS" REGISTER, AND THE RESULTING "M-BIT OOF DECLARATION CRITERIA"

USED BY THE

"RECEIVE DS3 FRAMER" BLOCK .......................................................................... 295

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ...................................................... 296

I/O CONTROL REGISTER (ADDRESS = 0X01) ............................................................................................. 296

PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52) .................................... 296

PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53) ..................................... 297

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ...................................................... 297

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ...................................................... 298

RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ...................................................... 299

RX DS3 STATUS REGISTER (ADDRESS = 0X11) ........................................................................................ 299

RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ....................................................................... 300

RXDS3 STATUS REGISTER (ADDRESS = 0X11) ......................................................................................... 300

RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ........................................................................ 301

PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54) ............................................. 301

PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55) .............................................. 301

Figure 101. A Simple Illustration of the Locations of the “Source”, “Mid-Network” and “Sink” Ter-

minal Equipment (for CP-Bit Processing) ......................................................................... 302

Figure 102. Illustration of the “Presumed Configuration” of the Mid-Network Terminal Equipment .

303

4.3.3 The Receive HDLC Controller Block .................................................................................................. 303

RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................... 304

RX DS3 FEAC REGISTER (ADDRESS = 0X16) .......................................................................................... 305

RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................... 305

Figure 103. Flow Diagram depicting how the Receive FEAC Processor Functions ..................... 306

Figure 104. LAPD Message Frame Format ........................................................................................ 307

RX DS3 LAPD CONTROL REGISTER (ADDRESS = 0X18) ........................................................................... 307

RX DS3 LAPD STATUS REGISTER (ADDRESS = 0X19) .............................................................................. 308

TABLE 34: THE RELATIONSHIP BETWEEN RXLAPDTYPE[1:0] AND THE RESULTING LAPD MESSAGE TYPE AND

SIZE

.......................................................................................................................................... 308

Figure 105. Flow Chart depicting the Functionality of the LAPD Receiver .................................... 310

4.3.4 The Receive Overhead Data Output Interface ................................................................................... 310

Figure 106. A Simple Illustration of the "Receive Overhead Output Interface" block .................. 311

TABLE 35: LISTING AND DESCRIPTION OF THE PIN ASSOCIATED WITH THE RECEIVE OVERHEAD DATA OUTPUT

INTERFACE" BLOCK .................................................................................................................. 312

Figure 107. Illustration of how to interface the Terminal Equipment to the “Receive Overhead Data

Output Interface” block (for Method 1). ............................................................................. 313

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