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XRT72L13 Datasheet(PDF) 73 Page - Exar Corporation |
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XRT72L13 Datasheet(HTML) 73 Page - Exar Corporation |
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73 / 370 page ![]() áç áç áç áç M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC XRT72L13 PRELIMINARY REV. 1.0.6 61 Figure 31 indicates that when the XRT72L13 has been configured to operate in the "Clear Channel DS3 Framer Remote Loop-back" Mode, then the fol- lowing internal connections are made: • The RxPOS input signal is routed to the TxPOS output pin. • The RxNEG input signal is routed to the TxNEG output pin. • The RxLineClk output clock signal is routed to the TxLineClk input pin. 1.2.1.1.3 PRBS Generator/Receiver In order to support diagnostic testing of the signal path, the XRT72L13 contains a PRBS Generator and Receiver. This feature can be operated in conjunc- tion with (or not) with the "Clear Channel DS3 Framer Local" or "Remote" Loop-back Modes. A more detailed description of this feature will be pre- sented in the next revision of the XRT72L13 Data Sheet. 1.3 XRT72L13 OPERATION WHILE IN THE "HIGH SPEED HDLC CONTROLLER" MODE Figure 32 presents a Functional Block Diagram of the XRT72L13 M13 Multiplexer/Framer IC, when it has been configured to operate in the "High Speed HDLC Controller Mode" FIGURE 31. ILLUSTRATION OF THE XRT72L13 M13 MULTIPLEXER/FRAMER OPERATING IN THE "CLEAR CHANNEL DS3 FRAMER REMOTE LOOP-BACK" MODE Transmit Payload Data Input Interface Block Transmit DS3 Framer Block Transmit LIU Interface Block Receive LIU Interface Block Receive DS3 Framer Block Receive Payload Data Output Interface Block Microprocessor Interface TxSer TxNib[3:0] TxInClk MOTO D[7:0] A[8:0] IntB* CSB* RdB_DS WrB_RW Rdy_Dtck Reset* ALE_AS RxSer RxNib[3:0] RxOutClk TxPOS TxNEG TxLineClk RxPOS RxNEG RxLineClk Tx LAPD Buffer/ Controller Rx LAPD Buffer/ Controller Transmit Overhead Input Interface Block Receive Overhead Output Interface Block TxOHClk TxOHIns TxOHInd TxOH TxOHEnable TxOHFrame TxNibClk TxFrame RxNibClk RxFrame RxOHFrame RxOH RxOHClk RxOHEnable RxOHInd Remote Loop-back Path |
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