XRT72L13 datasheet(87/370 Pages) EXAR

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13

PRELIMINARY

REV. 1.0.6

byte or word (to be written into the Framer) to

the bi-directional data bus pins, D[7:0].

B.2

Toggle the WRB_RW (Write Strobe) input pin

"low". This step accomplishes two things.

a. It enables the input drivers of the bi-directional

data bus.

b. It causes the Framer to internally increment the

value of the "latched" address.

B.3

After waiting the appropriate amount of settling

time the data, in the internal data bus, will stabi-

lize and is ready to be latched into the Framer

Microprocessor Interface block. At this point,

the µC/µP should latch the data into the Framer

by toggling the WRB_RW input pin "high".

For subsequent write operations, within this burst I/O

access, the µC/µP simply repeats steps B.1 through

B.3, as illustrated in Figure 41.

2.2.2.2.1.2.3

Terminating the Burst I/O Access

Burst Access Operation will be terminated upon the

rising edge of the ALE_AS input signal. At this point

the Framer will cease to internally increment the

"latched" address value. Further, the µC/µP is now

free to execute either a "Programmed I/O" access or

to start another "Burst Access Operation" with the

XRT 72L13 DS3 Framer.

2.2.2.2.2

Burst I/O Access in the Motorola

Mode

If the XRT 72L13 DS3 Framer is interfaced to a "Mo-

torola-type" µC/µP (e.g., the MC680x0 family, etc.),

then it should be configured to operate in the "Motor-

ola" mode (by tying the "MOTO" pin to VCC). Motoro-

la-type "Read" and "Write" Burst I/O Access opera-

tions are described below.

2.2.2.2.2.1

The "Motorola-Mode" Read Burst I/

O Access Operation

Whenever a "Motorola-type" µC/µP wishes to read

the contents of numerous registers or buffer locations

over a "contiguous" range of addresses, then it

should do the following.

a. Perform the initial "Read" operation of the burst

access.

b. Perform the remaining "read" operations; in the

burst access.

c. Terminate the "burst access" operation.

Each of these operations, within the Burst Access are

discussed below.

2.2.2.2.2.1.1

The Initial Read Operation

The initial read operation of a "Motorola-type" read

burst access is accomplished by executing a "Pro-

grammed I/O Read" cycle, as summarized below.

A.0

Execute a Single Ordinary (Programmed I/

O) Read Cycle, as described in steps A.1

through A.8 below.

A.1

Assert the ALE_AS (AS*) input pin by toggling

it "low". This step enables the "Address Bus"

input drivers (within the XRT 72L13 DS3

Framer) within the Framer Microprocessor

Interface Block.

A.2

Place the address of the "initial" target register

or buffer location (within the Framer), on the

Address Bus input pins, A[8:0].

A.3

At the same time, the Address-Decoding cir-

cuitry (within the user's system) should assert

the CS* (Chip Select) input pins of the Framer

FIGURE 41. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT "WRITE" OPERA-

TIONS WITHIN THE

BURST I/O CYCLE

ALE_AS

WRB_RW

A[8:0]

CS*

D[15:0]

Rdy_Dtck

Data Written at Offset =0x01

RDB_DS

Data Written at Offset =0x02

Address of “Initial” Target Register (Offset = 0x00)

XRT72L13 Datasheet(PDF) 87 Page - Exar Corporation

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