XRT72L13 datasheet(82/370 Pages) EXAR

82 / 370 page

XRT72L13

MULTIPLEXER/FRAMER IC

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PRELIMINARY

REV. 1.0.6

2.2.2.2

Data Access using Burst Mode I/O

Burst Mode I/O access is a much faster way to trans-

fer data between the µC/µP and the Microprocessor

Interface (of the XRT 72L13 DS3 Framer), than Pro-

grammed I/O. The reason why Burst Mode I/O is so

much faster follows.

Data is placed upon the Address Bus input pins

A[8:0]; only for the very first access, within a given

burst access. The remaining read or write operations

(within this burst access) do not require the place-

ment of the Address Data on the Address Data Bus.

As a consequence, the user does not have to wait

through the "Address Setup" and "Hold" times; for

each of these Read/Write operation, within the

"Burst" Access.

It is important to note that there are some limitations

associated with Burst Mode I/O Operations.

1. All cycles within the Burst Access, must be either

"all Read" or "all Write" cycles. No "mixing of

"Read" and "Write" cycles is permitted.

2. A Burst Access can only be used when "Read" or

"Write" operations are to be employed over a

contiguous range of address locations, within the

Framer device.

3. The very first "Read" or "Write" cycle, within a

burst access, must start at the "lowest" address

value, of the range of addresses to be accessed.

Subsequent operations will automatically be

incremented to the very next higher address

value.

Examples of Burst Mode I/O operations are present-

ed below for read and write operations, with both "In-

tel-type" and "Motorola-type" µC/µP.

2.2.2.2.1

Burst I/O Access in the Intel Mode

If the XRT 72L13 DS3 Framer is interfaced to an "In-

tel-type" µC/µP (e.g., the 80x86 family, etc.), then it

should be configured to operate in the "Intel" mode

(by tying the "MOTO" pin to ground). Intel-type

"Read" and "Write" Burst I/O Access operations are

described below.

2.2.2.2.1.1

The "Intel-Mode" Read Burst

Access

Whenever an "Intel-type" µC/µP wishes to read the

contents of numerous registers or buffer locations

over a "contiguous" range of addresses; then it

should do the following.

Perform the initial "read" operation of the burst

access.

b. Perform the remaining "read" operations of the

burst access.

c. Terminate the "burst access" operation.

Each of these "operations" within the burst access

are described below.

2.2.2.2.1.1.1

The Initial Read Operation

The initial read operation of an "Intel-type" read burst

access is accomplished by executing a "Programmed

I/O" Read Cycle as summarized below.

A.0

Execute a Single Ordinary (Programmed I/

O) Read Cycle, as described in steps A.1

through A.7 below.

A.1

Place the address of the "initial-target" register

or buffer location (within the Framer) on the

Address Bus input pins A[8:0].

A.2

While the µC/µP is placing this address value

onto the Address Bus, the Address Decoding

FIGURE 37. ILLUSTRATION OF THE BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNAL, DURING A "MOTOR-

OLA

-TYPE" PROGRAMMED I/O WRITE OPERATION

ALE_AS

A[8:0]

CS*

D[15:0]

RDB_DS

Rdy_Dtck

Data to be Written

Address of Target Register

WRB_RW

XRT72L13 Datasheet(PDF) 82 Page - Exar Corporation

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