XRT72L13 datasheet(91/370 Pages) EXAR

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M13 MULTIPLEXER/CLEAR CHANNEL DS3 FRAMER IC

XRT72L13

PRELIMINARY

REV. 1.0.6

For subsequent write operations, within this burst I/O

access, the µC/µP simply repeats steps B.1 through

B.3 as illustrated in Figure 45.

2.2.2.2.2.2.3

Terminating the Burst I/O Access

The Burst I/O Access will be terminated upon the fall-

ing edge of the ALE_AS input signal. At this point the

Framer will cease to internally increment the "latched"

address value. Further, the µC/µP is now free to exe-

cute either a "Programmed I/O" access or to start an-

other "Burst I/O Access" with the XRT72L13 DS3

Framer.

2.3

ON-CHIP REGISTER ORGANIZATION

The Microprocessor Interface section, within the

Framer device allows the user to do the following.

• Configure the Framer into a wide variety of operat-

ing modes.

• Employ various features of the Framer device.

• Perform status monitoring

• Enable/Disable and service Interrupt Conditions

All of these things are accomplished by reading from

and writing to the many on-chip registers within the

Framer device. Table 4 lists each of these registers

and their corresponding address locations within the

Framer Address space.

2.3.1

Framer Register Addressing

The array of on-chip registers consists of a variety of

Table 4, as follows.

R/O - Read Only Registers.

R/W - Read/Write Registers

RUR - Reset-upon-Read Registers

Additionally, some of these registers consists of both

"R/O" and "R/W" bit-fields. These registers are de-

noted in Table 4 as "Combination of R/W and R/O".

The bit-format and definitions for each of these regis-

ters are presented in Section 2.3.2

2.3.2

M13 Mux/Framer Register Description

This section provides a function description of each

bit-field within each of the on-chip Framer Register.

NOTE: For all on-chip registers, a table containing the bit-

format of the register is presented. Additionally, these

tables also contain the default values for each of these reg-

ister bits. Finally, the function description, associated with

each register bit-field is presented, along with a reference to

a Section Number, within this Data Sheet, that provides a

more in-depth discussion of the functions associated with

this register bit-field.

FIGURE 45. BEHAVIOR OF THE MICROPROCESSOR INTERFACE SIGNALS, DURING SUBSEQUENT "WRITE" OPERA-

TIONS WITH THE

BURST I/O CYCLE (MOTOROLA-TYPE µC/µP)

ALE_AS

RDB_DS

A[8:0]

CS*

D[15:0]

Rdy_Dtck

Data Written at Offset =0x01

WRB_RW

Data Written at Offset =0x02

Address of “Initial” Target Register (Offset = 0x00)

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