MSP430F449IPZ datasheet(39/85 Pages) TI

39 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

A/D converter

The 12-bit analog-to-digital converter (ADC) uses a 10-bit weighted capacitor array plus a 2-bit resistor string.

The CMOS threshold detector in the successive-approximation conversion technique determines each bit by

examining the charge on a series of binary-weighted capacitors. The features of the ADC are:

D 12-bit converter with ±1-LSB linearity

D Built-in sample-and-hold

D Eight external and four internal analog channels. The external ADC input terminals are shared with digital

port I/O pins.

D Internal reference voltage VREF+ of 1.5 V or 2.5 V, software-selectable by control bit 2_5V

D Internal-temperature sensor for temperature measurement:

–

T = [V_SENSOR(T) – V_SENSOR(0

°C)] / TC_SENSOR in °C

D Battery-voltage measurement: N = 0.5 × (AVCC – AVSS) × 4096/1.5 V; VREF+ is selected for 1.5 V.

D Source of positive reference voltage level (VR+) can be selected as internal (1.5 V or 2.5 V), external, or

AVCC. The source is selected individually for each channel.

D Source of negative reference voltage level (VR-) can be selected as external or AVSS. The source is selected

individually for each channel.

D Conversion time can be selected from various clock sources: ACLK, MCLK, SMCLK, or the internal

ADC12CLK oscillator. The clock source is divided by an integer from 1 to 8, as selected by software.

D Channel conversion: individual channels, a group of channels, or repeated conversion of a group of

channels. If conversion of a group of channels is selected, the sequence, the channels, and the number

of channels in the group can be defined by software. For example, a1-a2-a5-a2-a2-

….

D The conversion is enabled by the ENC bit, and can be triggered by software via sample and conversion

control bit ADC12SC, Timer_A3, or Timer_Bx. Most of the control bits can be modified only if the ENC

control bit is low. This prevents unpredictable results caused by unintended modification.

D Sampling time can be 4 × n0 × ADC12CLK or 4 × n1 × ADC12CLK. It can be selected to sample as long

as the sample signal is high (ISSH=0) or low (ISSH=1). SHT0 defines n0 and SHT1 defines n1.

D The conversion result is stored in one of 16 registers. The 16 registers have individual addresses and can

be accessed via software. Each of the 16 registers is linked to an 8-bit register that defines the positive and

negative reference source and the channel assigned.

MSP430F449IPZ Datasheet(PDF) 39 Page - Texas Instruments