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MSP430F449IPZ Datasheet(PDF) 20 Page - Texas Instruments |
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MSP430F449IPZ Datasheet(HTML) 20 Page - Texas Instruments |
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20 / 85 page  MSP430x43x, MSP430x44x MIXED SIGNAL MICROCONTROLLER SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002 20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 flash memory (continued) D During program or erase, no code can be executed from flash memory and all interrupts must be disabled by setting the GIE, NMIIE, ACCVIE, and OFIE bits to zero. If a user program requires execution concurrent with a flash program or erase operation, the program must be executed from memory other than the flash memory (e.g., boot ROM, RAM). In the event a flash program or erase operation is initiated while the program counter is pointing to the flash memory, the CPU will execute JMP $ instructions until the flash program or erase operation is completed. Normal execution of the previously running software then resumes. D Unprogrammed, new devices may have some bytes programmed in the information memory (needed for test during manufacturing). The user should perform an erase of the information memory prior to the first use. Segment 0 w/ Interrupt Vectors Segment 1 Segment 2 Segment n-1 Segment n Segment A Segment B Main Memory Information Memory 24KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 16KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 32KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 48KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 60KB 0FFFFh 0FE00h 0FDFFh 0FC00h 0FBFFh 0FA00h 0F9FFh 0A400h 0A3FFh 0A200h 0A1FFh 0A000h 010FFh 01080h 0107Fh 01000h 0C400h 0C3FFh 0C200h 0C1FFh 0C000h 010FFh 01080h 0107Fh 01000h 08400h 083FFh 08200h 081FFh 08000h 010FFh 01080h 0107Fh 01000h 04400h 043FFh 04200h 041FFh 04000h 010FFh 01080h 0107Fh 01000h 01400h 013FFh 01200h 011FFh 01100h 010FFh 01080h 0107Fh 01000h flash memory, control register FCTL1, FCTL2, and FCTL3 All control bits are reset during PUC. PUC is active after VCC is applied, a reset condition is applied to the RST/NMI pin or the Watchdog Timer expires, a watchdog access violation occurs, or an improper flash operation has been performed. Any write to control register FCTL1 during erase, mass erase, or write (programming) ends in an access violation with ACCVIFG=1. In an active segment write mode the control register may be written if wait mode is active (WAIT=1). Read access is possible at any time without restrictions. The control bits of control register FCTL1 hold all bits that apply write (programming) or erase modes. Writing to the control register requires key word 0A5H in the high-byte. Any other data there generates a power-up clear (PUC) which resets the controller. |
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