MSP430F449IPZ datasheet(53/85 Pages) TI

53 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted)

input frequency – ports P1, P2, P3, P4, P5, and P6

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f(IN)

t(h) t(L)

VCC = 2.2 V

MHz

f(IN)

t(h) = t(L)

VCC = 3 V

MHz

capture timing _ Timer_A3: TA0, TA1, TA2; Timer_B7: TB0 to TB6

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

P t P2 P4

VCC = 2.2 V/3 V

1.5

Cycle

t(int)

Ports P2, P4:

External trigger signal for the interrupt flag (see Note 1 and Note 2)

VCC = 2.2 V

(int)

External trigger signal for the interrupt flag (see Note 1 and Note 2)

VCC = 3 V

NOTES:

1. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).

The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.

2. The external signal needs additional timing because of the maximum input-frequency constraint.

output frequency

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

≤ ≤ 60 ≤ ≤ 7)

CL = 20 pF,

VCC = 2.2 V

f(Px.y)

≤ x ≤ 6, 0 ≤ y ≤ 7)

CL = 20 F,

IL = ±1.5mA

VCC = 3 V

7.5

MHz

f(ACLK)

P1 1/TA0/MCLK P1 5/TACLK/

f(MCLK)

P1.1/TA0/MCLK, P1.5/TACLK/

ACLK P1 4/TBCLK/SMCLK

CL = 20 pF

f(System)

MHz

f(SMCLK)

ACLK P1.4/TBCLK/SMCLK

CL 20 F

f(System)

MHz

P1.5/TACLK/ACLK,

f(ACLK) = f(LFXT1) = f(XT1)

40%

60%

P1.5/TACLK/ACLK,

CL = 20 pF

f(ACLK) = f(LFXT1) = f(LF)

30%

70%

CL 20 F

VCC = 2.2 V / 3 V

f(ACLK) = f(LFXT1)

50%

P1.1/TA0/MCLK,

f(MCLK) = f(XT1)

40%

60%

t(Xdc)

Duty cycle of output frequency

P1.1/TA0/MCLK,

CL = 20 pF,

VCC = 2.2 V / 3 V

f(MCLK) = f(DCOCLK)

50%–

15 ns

50%

50%+

15 ns

P1.4/TBCLK/SMCLK,

f(SMCLK) = f(XT2)

40%

60%

P1.4/TBCLK/SMCLK,

CL = 20 pF,

VCC = 2.2 V / 3 V

f(SMCLK) = f(DCOCLK)

50%–

15 ns

50%

50%+

15 ns

external interrupt timing

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

P t P1 P2

VCC = 2.2 V/3 V

1.5

Cycle

t(int)

Ports P1, P2:

External trigger signal for the interrupt flag (see Note 3 and Note 4)

VCC = 2.2 V

(int)

External trigger signal for the interrupt flag (see Note 3 and Note 4)

VCC = 3 V

NOTES:

3. The external signal sets the interrupt flag every time t(int) is met. It may be set even with trigger signals shorter than t(int).

The conditions to set the flag must be met independently of this timing constraint. t(int) is defined in MCLK cycles.

4. The external signal needs additional timing because of the maximum input-frequency constraint.

wake-up LPM3

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

f = 1 MHz

td(LPM3)

Delay time

f = 2 MHz

VCC = 2.2 V/3 V

µs

td(LPM3)

Delay time

f = 3 MHz

VCC 2.2 V/3 V

µs

MSP430F449IPZ Datasheet(PDF) 53 Page - Texas Instruments

MSP430F449IPZ Datasheet(HTML) 53 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL