MSP430F449IPZ datasheet(25/85 Pages) TI

25 / 85 page

MSP430x43x, MSP430x44x

MIXED SIGNAL MICROCONTROLLER

SLAS344A – JANUARY 2002 – REVISED FEBRUARY 2002

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

oscillator and system clock (continued)

The ACLK is defined by connecting a low-power, low-frequency, or high-frequency crystal to the oscillator, or

by applying an external clock source (XTS_FLL must be set). The crystal oscillator may be switched off when

the ACLK oscillator is not needed for the present operation mode.

The software selects the DCOCLK frequency. The DCOCLK is active if SCG1 is reset and stopped if SCG1 is

set. The dc generator can be stopped when SCG0 and SCG1 are set. The dc generator, which defines the basic

DCO frequency, can be adjusted in five steps using control bits FN_2, FN_3, FN_4, and FN_8.

When the target frequency needs modification of the FN_x bits, increasing D or setting DCO+, the following

sequence ensures that the maximum system frequency [f(system)] is not exceeded:

Save FLL lock bit (SCG0 in status register) and set it; loop control goes off.

Load modulation control register SCFQCTL with new data (modulation bit M, multiply factor N).

Set DCO control bits and MSB’s of modulator: SCFI1 = 0Fh to lowest possible frequency.

Select DCO+ control bit to be set or reset.

Load control register SCFI0 with new data.

Restore or set/reset the FLL control bit.

NOTE:

The system clock generator starts with the DCOCLK for MCLK (CPU clock) and program execution

starts quickly. The software defines the ACLK clock generation through control bit manipulation.

The MCLK is selected from DCOCLK (SELM {0,1}), XT2CLK (SELM=2), or ACLK (SELM=3). The initial source

for MCLK is DCOCLK. The SMCLK selects between two clock sources, the DCOCLK (SELS=0, initial state)

and XT2CLK (SELS=1). The XT2CLK is defined by connecting a high-frequency crystal to the oscillator (XT2IN,

XT2OUT), or by applying an external clock source to XT2IN. The crystal oscillator may be switched off when

the XT2 oscillator is not needed for the present operation mode.

The start conditions for MCLK and SMCLK frequency are identical to the FLL in MSP430x3xx devices, but the

correct capacitors at pin XIN and XOUT have to be selected with OscCap bits in register FLL+CTL0 at address

053h.

The ACLK, supplied for external use via port P1.5, may be divided by 1, 2, 4, or 8. This ensures clock signal

compatibility to the MSP430x3xx and MSP430x4xx families.

MSP430F449IPZ Datasheet(PDF) 25 Page - Texas Instruments