TMS320VC5416 datasheet(5/98 Pages) TI

5 / 98 page

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TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

List of Figures

2-1

144-Ball GGU MicroStar BGA™ (Bottom View)

............................................................................. 10

2-2

144-Pin PGE Low-Profile Quad Flatpack (Top View)

....................................................................... 12

3-1

TMS320VC5416 Functional Block Diagram

.................................................................................. 16

3-2

Program and Data Memory Map

................................................................................................ 20

3-3

Extended Program Memory Map

............................................................................................... 21

3-4

Process Mode Status Register

.................................................................................................. 22

3-5

Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

......................... 23

3-6

Software Wait-State Register (SWWSR) [Memory-Mapped Register (MMR) Address 0028h]

......................... 24

3-7

Bank-Switching Control Register BSCR)[MMR Address 0029h]

........................................................... 25

3-8

Host-Port Interface — Nonmulltiplexed Mode

................................................................................. 28

3-9

HPI Memory Map

................................................................................................................. 29

3-10

Multichannel Control Register (MCR1)

......................................................................................... 31

3-11

Multichannel Control Register (MCR2)

......................................................................................... 31

3-12

Pin Control Register (PCR)

...................................................................................................... 32

3-13

Nonconsecutive Memory Read and I/O Read Bus Sequence

............................................................. 34

3-14

Consecutive Memory Read Bus Sequence (n = 3 reads)

.................................................................. 35

3-15

Memory Write and I/O Write Bus Sequence

................................................................................. 36

3-16

DMA Transfer Mode Control Register (DMMCRn)

........................................................................... 37

3-17

On-Chip DMA Memory Map for Program Space (DLAXS = 0 and SLAXS = 0)

......................................... 39

3-18

On-Chip DMA Memory Map for Data and IO Space (DLAXS = 0 and SLAXS = 0)

.................................... 40

3-19

DMPREC Register

................................................................................................................ 41

3-20

General-Purpose I/O Control Register (GPIOCR) [MMR Address 003Ch]

................................................ 44

3-21

General-Purpose I/O Status Register (GPIOSR) [MMR Address 003Dh]

................................................. 44

3-22

Device ID Register (CSIDR) [MMR Address 003Eh]

......................................................................... 44

3-23

IFR and IMR Registers

........................................................................................................... 50

5-1

Tester Pin Electronics

............................................................................................................ 54

5-2

Internal Divide-By-Two Clock Option With External Crystal

............................................................... 56

5-3

External Divide-By-Two Clock Timing

......................................................................................... 58

5-4

Multiply-By-One Clock Timing

.................................................................................................. 59

5-5

Nonconsecutive Mode Memory Reads

....................................................................................... 61

5-6

Consecutive Mode Memory Reads

............................................................................................ 62

5-7

Memory Write (MSTRB = 0)

.................................................................................................... 63

5-8

Parallel I/O Port Read (IOSTRB = 0)

......................................................................................... 65

5-9

Parallel I/O Port Write (IOSTRB = 0)

.......................................................................................... 66

5-10

Memory Read With Externally Generated Wait States

..................................................................... 68

5-11

Memory Write With Externally Generated Wait States

..................................................................... 69

5-12

I/O Read With Externally Generated Wait States

........................................................................... 70

5-13

I/O Write With Externally Generated Wait States

........................................................................... 71

5-14

HOLD and HOLDA Timings (HM = 1)

......................................................................................... 73

List of Figures

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