TMS320VC5416 datasheet(30/98 Pages) TI

30 / 98 page

www.ti.com

3.8

Multichannel Buffered Serial Ports (McBSPs)

TMS320VC5416

Fixed-Point Digital Signal Processor

SPRS095O – MARCH 1999 – REVISED JANUARY 2005

The device provides three high-speed, full-duplex, multichannel buffered serial ports that allow direct

interface to other C54x/LC54x devices, codecs, and other devices in a system. The McBSPs are based on

the standard serial-port interface found on other 54x devices. Like their predecessors, the McBSPs

provide:

• Full-duplex communication

• Double-buffer data registers, which allow a continuous data stream

• Independent framing and clocking for receive and transmit

In addition, the McBSPs have the following capabilities:

• Direct interface to:

–

T1/E1 framers

–

MVIP switching compatible and ST-BUS compliant devices

–

IOM-2 compliant devices

–

AC97-compliant devices

–

IIS-compliant devices

–

Serial peripheral interface

• Multichannel transmit and receive of up to 128 channels

• A wide selection of data sizes, including 8, 12, 16, 20, 24, or 32 bits

• µ-law and A-law companding

• Programmable polarity for both frame synchronization and data clocks

• Programmable internal clock and frame generation

The McBSP consists of a data path and control path. The six pins, BDX, BDR, BFSX, BFSR, BCLKX, and

BCLKR, connect the control and data paths to external devices. The implemented pins can be

programmed as general-purpose I/O pins if they are not used for serial communication.

The data is communicated to devices interfacing to the McBSP by way of the data transmit (BDX) pin for

transmit and the data receive (BDR) pin for receive. The CPU or DMA reads the received data from the

data receive register (DRR) and writes the data to be transmitted to the data transmit register (DXR). Data

written to the DXR is shifted out to BDX by way of the transmit shift register (XSR). Similarly, receive data

on the BDR pin is shifted into the receive shift register (RSR) and copied into the receive buffer register

(RBR). RBR is then copied to DRR, which can be read by the CPU or DMA. This allows internal data

movement and external data communications simultaneously.

Control information in the form of clocking and frame synchronization is communicated by way of BCLKX,

BCLKR, BFSX, and BFSR. The device communicates to the McBSP by way of 16-bit-wide control

registers accessible via the internal peripheral bus.

The control block consists of internal clock generation, frame synchronization signal generation, and their

control, and multichannel selection. This control block sends notification of important events to the CPU

and DMA by way of two interrupt signals, XINT and RINT, and two event signals, XEVT and REVT.

The on-chip companding hardware allows compression and expansion of data in either µ-law or A-law

format. When companding is used, transmitted data is encoded according to the specified companding

law and received data is decoded to 2s complement format.

The sample rate generator provides the McBSP with several means of selecting clocking and framing for

both the receiver and transmitter. Both the receiver and transmitter can select clocking and framing

independently.

Functional Overview

TMS320VC5416 Datasheet(PDF) 30 Page - Texas Instruments

TMS320VC5416 Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98

Datasheet Download

Link URL