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WM8595 Datasheet(PDF) 59 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 59 Page - Wolfson Microelectronics plc |
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59 / 82 page ![]() Production Data WM8595 w PD, Rev 4.2, January 2011 59 R14 (0Eh) – ADC Control Register 2 (ADC_CTRL2) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 0 ADC_BCLKDIV[2:0] ADC_SR[2:0] Write N/A N/A Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description ADC_SR[2:0] ADC MCLK:LRCLK Ratio 000 = Auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved ADC_BCLKDIV[2:0] ADC BCLK Rate (when ADC in Master Mode) 000 = MCLK / 4 001 = MCLK / 8 010 = 32fs 011 = 64fs 100 = 128fs All other values of ADC_BCLKDIV[2:0] are reserved Figure 36 R14 – ADC Control Register 2 R15 (0Fh) – ADC Control Register 3 (ADC_CTRL3) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 0 0 0 Write N/A N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 0 0 0 0 0 0 ADC_MSTR Write N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description ADC_MSTR ADC Master Mode Select 0 = Slave mode, ADCBCLK and ADCLRCLK are inputs to WM8595 1 = Master mode, ADCBCLK and ADCLRCLK are outputs from WM8595 Figure 37 R15 – ADC Control Register 3 |
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