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WM8595 Datasheet(PDF) 27 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 27 Page - Wolfson Microelectronics plc |
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27 / 82 page  Production Data WM8595 w PD, Rev 4.2, January 2011 27 SLAVE MODE In slave mode, the master clock to left/right clock ratio for the ADC, DAC1 and DAC2 can be auto- detected or set manually by register write. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R3 DAC1_CTRL2 03h 2:0 DAC1_ SR[2:0] 000 DAC MCLK:LRCLK Ratio 000 = Auto detect 001 = 128fs 010 = 192fs 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = 1152fs R8 DAC2_CTRL2 08h 2:0 DAC2_ SR[2:0] 000 R14 ADC_CTRL2 0Eh 2:0 ADC_ SR[2:0] 000 ADC MCLK:LRCLK Ratio 000 = Auto detect 001 = reserved 010 = reserved 011 = 256fs 100 = 384fs 101 = 512fs 110 = 768fs 111 = Reserved Table 13 Slave Mode MCLK to LRCLK Ratio Control |
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