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WM8595 Datasheet(PDF) 72 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 72 Page - Wolfson Microelectronics plc |
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72 / 82 page  WM8595 Production Data w PD, Rev 4.2, January 2011 72 R44 (2Ch) – Audio Interface MUX Configuration Register 5 (AIF_MUX5) Bit # 15 14 13 12 11 10 9 8 Read 0 0 0 0 0 ADC_UPD 0 0 Write N/A N/A N/A N/A N/A N/A N/A Default 0 0 0 0 0 0 0 0 Bit # 7 6 5 4 3 2 1 0 Read 0 ADCWORDCLK_SEL[2:0] ADCMCLK_SEL[2:0] 0 Write N/A N/A Default 0 0 0 0 0 0 0 0 N/A = Not Applicable (no function implemented) Function Description ADCMCLK_SEL[2:0] ADCMCLK Select 000 = Use MCLK1 001 = Use MCLK2 010 to 111 = Reserved ADCWORDCLK_ SEL[2:0] ADCBCLK and ADCLRCLK Select 000 = Use BCLK1 and LRCLK1 001 = Use BCLK2 and LRCLK2 010 to 110 = Reserved 111 = Output ADCBCLK and ADCBCLK (when ADC is master mode) ADC_UPD ADC Clock Update 0 = Latch corresponding ADC clock settings into Register Map but do not update 1 = Latch corresponding ADC clock settings into Register Map and update all simultaneously Figure 53 R44 – Audio Interface MUX Configuration Register 5 |
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