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WM8595 Datasheet(PDF) 15 Page - Wolfson Microelectronics plc |
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WM8595 Datasheet(HTML) 15 Page - Wolfson Microelectronics plc |
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15 / 82 page ![]() Production Data WM8595 w PD, Rev 4.2, January 2011 15 CONTROL INTERFACE TIMING – 3-WIRE MODE Figure 6 Control Interface Timing – 3-Wire Serial Control Mode Test Conditions AVDD1, DVDD = 3.3V, AVDD2 = 9V, AGND1, AGND2, DGND = 0V, TA = +25˚C, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Program Register Input Information SCLK rising edge to CS ¯ ¯ rising edge tSCS 80 ns SCLK pulse cycle time tSCY 160 ns SCLK duty cycle 40/60 60/40 % SDA to SCLK set-up time tDSU 20 ns SDA hold time from SCLK rising edge tDHO 40 ns SDOUT propagation delay from SCLK falling edge tDL 5 ns CS ¯ ¯ pulse width high tCSH 40 ns CS ¯ ¯ falling to SCLK rising tCSS1 40 ns SCLK failing to CS ¯¯ rising tCSS2 40 ns Pulse width of spikes that will be suppressed tps 2 8 ns Table 6 Control Interface Timing – 3-Wire Serial Control Mode |
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