WM8595 datasheet(24/82 Pages) WOLFSON

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WM8595

Production Data

PD, Rev 4.2, January 2011

DSP MODE B

In DSP Mode B, the MSB of channel 1 left data input is sampled on the first bit clock rising edge

following a left/right clock rising edge. Channel 1 right data then follows. The MSB of output data

changes on the same falling edge of BCLK as the low to high left/right clock transition and may be

sampled on the rising edge of bit clock. The right channel data is contiguous with the left channel

data.

Figure 17 DSP Mode B Timing

DIGITAL AUDIO INTERFACE CONTROL

The control of the audio interface formats is achieved by register write. Dynamically changing the

audio data format may cause erroneous operation and is not recommended.

Interface timing is such that the input data and left/right clock are sampled on the rising edge of the

interface bit clock. Output data changes on the falling edge of the interface bit clock. By setting the

appropriate bit clock and left/right clock polarity bits, the WM8595 ADC and DACs can sample data

on the opposite clock edges.

The control of audio interface formats and clock polarities is summarised in Table 11.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

DAC1_CTRL1

02h

1:0

DAC1_

FMT[1:0]

DAC1 Audio Interface Format

00 = Right Justified

01 = Left Justified

10 = I2S

11 = DSP

3:2

DAC1_

WL[1:0]

DAC1 Audio Interface Word Length

00 = 16-bit

01 = 20-bit

10 = 24-bit

11 = 32-bit (not available in Right Justified

mode)

DAC1_BCP

DAC1 BCLK Polarity

0 = DACBCLK not inverted - data latched on

rising edge of BCLK

1 = DACBCLK inverted - data latched on

falling edge of BCLK

WM8595 Datasheet(PDF) 24 Page - Wolfson Microelectronics plc

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