WM8595 datasheet(70/82 Pages) WOLFSON

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WM8595

Production Data

PD, Rev 4.2, January 2011

R42 (2Ah) – Audio Interface MUX Configuration Register 3 (AIF_MUX3)

Bit #

Read

DAC1_UPD

DAC1DIN_SEL[2:1]

Write

N/A

Default

Bit #

Read

DAC1DIN_

SEL[0]

DAC1WORDCLK_SEL[2:0]

DAC1MCLK_SEL[2:0]

Write

N/A

Default

N/A = Not Applicable (no function implemented)

Function

Description

DAC1MCLK_SEL[2:0]

DAC1MCLK Select

000 = Use MCLK1

001 = Use MCLK2

010 to 111 = Reserved

DAC1WORDCLK_

SEL[2:0]

DAC1BCLK and DAC1LRCLK Select

000 = Use BCLK1 and LRCLK1

001 = Use BCLK2 and LRCLK2

010 to 110 = Reserved

111 = Use ADCBCLK and ADCBCLK (when ADC is master mode)

DAC1DIN_SEL[2:0]

DAC1DIN Select

000 = Use DACDAT1

001 = Use DACDAT2

010 to 100 = Reserved

101 = Use GPIO1

110 = Use GPIO2

111 = Reserved

DAC1_UPD

DAC1 Clock Update

0 = Latch corresponding DAC1 clock settings into Register Map but do not update

1 = Latch corresponding DAC1 clock settings into Register Map and update all simultaneously

Figure 51 R42 – Audio Interface MUX Configuration Register 3

WM8595 Datasheet(PDF) 70 Page - Wolfson Microelectronics plc

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