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TMS320VC5407 Datasheet(PDF) 52 Page - Texas Instruments |
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TMS320VC5407 Datasheet(HTML) 52 Page - Texas Instruments |
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52 / 110 page  Functional Overview 52 November 2001 − Revised April 2004 SPRS007D 3.13.1 UART Accessible Registers The system programmer has access to and control over any of the UART registers that are summarized in Table 3−14. These registers control UART operations, receive data, and transmit data. Descriptions of these registers follow Table 3−15. See Table 3−24 for more information on peripheral memory mapped registers. Table 3−15. Summary of Accessible Registers UART SUBBANK ADDRESS 0 (DLAB = 0) 0 (DLAB = 0) 0 (DLAB = 1) or 8 1 (DLAB = 0) 1 (DLAB = 1) or 9 2 2 3 4 5 6 7 BIT NO. Receiver Buffer Register (Read Only) Transmitter Holding Register (Write Only) Divisor Latch (LSB) Interrupt Enable Register Divisor Latch (MSB) Interrupt Ident. Register (Read Only) FIFO Control Register (Write Only) Line Control Register Modem Control Register Line Status Register Re- served Register Scratch Register RBR THR DLL IER DLM IIR FCR LCR MCR LSR RSV SCR 0 Data Bit 0† Data Bit 0 Bit 0 Enable Received Data Available Interrupt (ERBI) Bit 8 0 if Interrupt Pending FIFO Enable Word Length Select Bit 0 (WLS0) X Data Ready (DR) X Bit 0 1 Data Bit 1 Data Bit 1 Bit 1 Enable Transmitter Holding Register Empty Interrupt (ETBEI) Bit 9 Interrupt ID Bit 1 Receiver FIFO Reset Word Length Select Bit 1 (WLS1) X Overrun Error (OE) X Bit 1 2 Data Bit 2 Data Bit 2 Bit 2 Enable Receiver Line Status Interrupt (ELSI) Bit 10 Interrupt ID Bit 2 Transmitter FIFO Reset Number of Stop Bits (STB) X Parity Error (PE) X Bit 2 3 Data Bit 3 Data Bit 3 Bit 3 0‡ Bit 11 Interrupt ID Bit 3§ 0‡ Parity Enable (PEN) X Framing Error (FE) X Bit 3 4 Data Bit 4 Data Bit 4 Bit 4 0 Bit 12 0 Reserved Even Parity Select (EPS) Loop Break Interrupt (BI) X Bit 4 5 Data Bit 5 Data Bit 5 Bit 5 0 Bit 13 0 Reserved Stick Parity 0‡ Transmitter Holding Register (THRE) X Bit 5 6 Data Bit 6 Data Bit 6 Bit 6 0 Bit 14 FIFOs Enabled§ Receiver Trigger (LSB) Break Control 0 Transmitter Empty (TEMT) X Bit 6 7 Data Bit 7 Data Bit 7 Bit 7 0 Bit 15 FIFOs Enabled§ Receiver Trigger (MSB) Divisor Latch Access Bit (DLAB) 0 Error in RCVR FIFO§ X Bit 7 8 − 15 0 0 0 0 0 0 0 0 0 0 0 0 † Bit 0 is the least significant bit. It is the first bit serially transmitted or received. ‡ Must always be written as zero. § These bits are always 0 in the TL16C450 mode. NOTE: X = Don’t care for write, indeterminate on read. |
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