TMS320VC5407 datasheet(14/110 Pages) TI

14 / 110 page

Introduction

November 2001 − Revised April 2004

SPRS007D

Introduction

This data manual discusses features and specifications of the TMS320VC5407 and TMS320VC5404

(hereafter referred to as the 5407/5404 unless otherwise specified) digital signal processors (DSPs). The 5407

and 5404 are essentially the same device except for differences in their memory maps.

This section lists the pin assignments and describes the function of each pin. This data manual also provides

a detailed description section, electrical specifications, parameter measurement information, and mechanical

data about the available packaging.

NOTE: This data manual is designed to be used in conjunction with the TMS320C54x DSP Functional

Overview (literature number SPRU307).

2.1

Description

The 5407/5404 are based on an advanced modified Harvard architecture that has one program memory bus

and three data memory buses. These processors provide an arithmetic logic unit (ALU) with a high degree

of parallelism, application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The

basis of the operational flexibility and speed of these DSPs is a highly specialized instruction set.

Separate program and data spaces allow simultaneous access to program instructions and data, providing

a high degree of parallelism. Two read operations and one write operation can be performed in a single cycle.

Instructions with parallel store and application-specific instructions can fully utilize this architecture. In

addition, data can be transferred between data and program spaces. Such parallelism supports a powerful

set of arithmetic, logic, and bit-manipulation operations that can all be performed in a single machine cycle.

These DSPs also include the control mechanisms to manage interrupts, repeated operations, and function

calls.

2.2

Pin Assignments

Figure 2−1 illustrates the ball locations for the 144-pin ball grid array (BGA) package and is used in conjunction

with Table 2−1 to locate signal names and ball grid numbers. Figure 2−2 provides the pin assignments for the

144-pin low-profile quad flatpack (LQFP) package.

TMS320C54x is a trademark of Texas Instruments.

TMS320VC5407 Datasheet(PDF) 14 Page - Texas Instruments