TMS320VC5407 datasheet(79/110 Pages) TI

79 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

5.8.2 Memory Write

Table 5−10 assumes testing over recommended operating conditions with MSTRB = 0 and H = 0.5tc(CO) (see

Figure 5−7).

Table 5−10. Memory Write Switching Characteristics

PARAMETER

MIN

MAX

UNIT

Delay time, CLKOUT low to address

For accesses not immediately following a

HOLD operation

− 1

td(CLKL-A)

Delay time, CLKOUT low to address

valid†

For read accesses immediately following a

HOLD operation

− 1

Setup time, address valid before MSTRB

For accesses not immediately following a

HOLD operation

2H − 3

tsu(A)MSL

Setup time, address valid before MSTRB

low†

For read accesses immediately following a

HOLD operation

2H − 5

td(CLKL-D)W

Delay time, CLKOUT low to data valid

− 1

tsu(D)MSH

Setup time, data valid before MSTRB high

2H − 5

2H + 6

th(D)MSH

Hold time, data valid after MSTRB high

2H − 5

2H + 6

td(CLKL-MSL)

Delay time, CLKOUT low to MSTRB low

− 1

tw(SL)MS

Pulse duration, MSTRB low

2H − 2

td(CLKL-MSH)

Delay time, CLKOUT low to MSTRB high

† Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

TMS320VC5407 Datasheet(PDF) 79 Page - Texas Instruments

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