 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
TMS320VC5407 Datasheet(PDF) 67 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
TMS320VC5407 Datasheet(HTML) 67 Page - Texas Instruments |
|
|
67 / 110 page  Functional Overview 67 November 2001 − Revised April 2004 SPRS007D 3.19.1 IFR and IMR Registers The bit layout of the interrupt flag register (IFR) and the interrupt mask register (IMR) is shown in Figure 3−26. 15 14 13 12 11 10 9 8 Reserved UART DMAC5 DMAC4 BXINT1 BRINT1 HINT INT3† 7 65 43 21 0 BXINT2 BRINT2 BXINT0 BRINT0 TINT0 INT2 INT1 INT0 † Bit 8 reflects the status of either INT3 or TINT1: these two interrupts are ORed together. To distinguish one from the other, one of these two interrupt sources must be inhibited. Figure 3−26. IFR and IMR |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
