TMS320VC5407 datasheet(83/110 Pages) TI

83 / 110 page

Electrical Specifications

November 2001 − Revised April 2004

SPRS007D

5.8.4 I/O Write

Table 5−13 assumes testing over recommended operating conditions, IOSTRB = 0, and H = 0.5tc(CO) (see

Figure 5−9).

Table 5−13. I/O Write Switching Characteristics

PARAMETER

MIN

MAX

UNIT

Delay time, CLKOUT low to address

For accesses not immediately following a

HOLD operation

− 1

td(CLKL-A)

Delay time, CLKOUT low to address

valid†

For read accesses immediately following a

HOLD operation

− 1

Setup time, address valid before IOSTRB

For accesses not immediately following a

HOLD operation

2H − 3

tsu(A)IOSL

Setup time, address valid before IOSTRB

low†

For read accesses immediately following a

HOLD operation

2H − 5

td(CLKL-D)W

Delay time, CLKOUT low to write data valid

− 1

tsu(D)IOSH

Setup time, data valid before IOSTRB high

2H − 5

2H + 6

th(D)IOSH

Hold time, data valid after IOSTRB high

2H − 5

2H + 6

td(CLKL-IOSL)

Delay time, CLKOUT low to IOSTRB low

− 1

tw(SL)IOS

Pulse duration, IOSTRB low

2H − 2

td(CLKL-IOSH)

Delay time, CLKOUT low to IOSTRB high

† Address R/W, PS, DS, and IS timings are included in timings referenced as address.

td(CLKL-D)W

CLKOUT

A[22:0]†

D[15:0]

IOSTRB

R/W†

IS†

td(CLKL-D)W

tsu(D)IOSH

th(D)IOSH

tsu(A)IOSL

tw(SL)IOS

td(CLKL-IOSL)

td(CLKL-IOSH)

td(CLKL-A)

† Address, R/W, PS, DS, and IS timings are all included in timings referenced as address.

Figure 5−9. Parallel I/O Port Write (IOSTRB = 0)

TMS320VC5407 Datasheet(PDF) 83 Page - Texas Instruments

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