LAN89218 datasheet(41/148 Pages) MICROCHIP

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DS60001255B-page 41

LAN89218

A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was detected, will return

LAN89218 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required

to check the READY bit and verify that it is set before attempting any other reads or writes of the device.

Once the READY bit is set, the LAN89218 is ready to resume normal operation. At this time the WUPS field can be

cleared.

3.10.2.2

D2 Sleep

In this state, as shown in Table 3-11, all clocks to the MAC and host bus are disabled and the PHY is placed in a

reduced power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY (Mode Control/Status

READY bit in PMT_CTRL is cleared when entering the D2 state.

If properly enabled via the ED_EN and PME_EN bits, the LAN89218 will assert the PME hardware signal upon

detection of a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the LAN89218 to the

D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY

bit and verify that it is set before attempting any other reads or writes of the device. Before the LAN89218 is fully

awake from this state the EDPWRDOWN bit in register 17 of the PHY must be cleared in order to wake the PHY.

Do not attempt to clear the EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the

LAN89218 is ready to resume normal operation. At this time the WUPS field can be cleared.

3.10.2.3

Power Management Event Indicators

Figure 3-19 is a simplified block diagram of the logic that controls the external PME, and internal pme_interrupt

signals. The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, if enabled,

will generate a host interrupt upon detection of a power management event. The PME_INT status bit in INT_STS

will remain set until the internal pme_interrupt signal is cleared by clearing the WUPS bits, or by clearing the

corresponding WOL_EN or ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may

Note:

The host must only perform read accesses prior to the ready bit being set.

Note:

If carrier is present when this state is entered detection will occur immediately.

Note:

The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the setting of

PME_EN.

TABLE 3-11:

POWER MANAGEMENT STATES

Device

BLOCK

(NORMAL

OPERATION)

(WOL)

(ENERGY DETECT)

PHY

Full ON

Energy Detect Power-Down

MAC Power Management

Full ON

RX Power Mgmt. Block On

OFF

MAC and Host Interface

Full ON

OFF

Internal Clock

Full ON

OFF

KEY:

CLOCK ON

BLOCK DISABLED – CLOCK ON

FULL OFF

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