LAN89218 datasheet(82/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 82

 2008-2015 Microchip Technology Inc.

5.3.9

HW_CFG—HARDWARE CONFIGURATION REGISTER

Offset:

74h

Size:

32 bits

Note:

The transmitter and receiver must be stopped before writing to this register. Refer to Section 3.12.8 and

Section 3.13.4 for details on stopping the transmitter and receiver.

Bits

Description

Type

Default

31:25

Reserved

AMDIX_EN Strap State. This read-only bit reflects the state of the AMDIX-

_EN strap pin (pin 73). This pin can be overridden by PHY Registers 27.15

and 27.13.

AMDIX

Strap

23:21

Reserved

Must Be One (MBO). This bit must be set to “1” for normal device operation.

R/W

19:16

TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1 kB values to a

maximum of 14 kB. The TX Status FIFO consumes 512 bytes of the space

allocated by TX_FIF_SIZ, and the TX data FIFO consumes the remaining

space specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2 kB

(TX data and status combined). The TX data FIFO is used for both TX data

and TX commands.

The RX status and data FIFOs consume the remaining space, which is equal

to 16 kB – TX_FIF_SIZ. See Section 5.3.9.1 for more information.

R/W

15:3

Reserved

32/16-bit Mode. When set, the LAN89218 is set for 32-bit operation. When

clear, it is configured for 16-bit operation. This field is the value of the D32/

nD16 strap.

Soft Reset Time-out (SRST_TO). If a software reset is attempted when the

internal PHY is not in the operational state (RX_CLK and TX_CLK running),

the reset will not complete and the soft reset operation will time-out and this

bit will be set to a ‘1’. The host processor must correct the problem and issue

another soft reset.

Soft Reset (SRST). Writing 1 generates a software initiated reset. This reset

generates a full reset of the MAC CSR’s. The SCSRs (system command and

status registers) are reset except for any NASR bits. Soft reset also clears

any TX or RX errors (TXE/RXE). This bit is self-clearing.

Note:

Do not attempt a soft reset unless the internal PHY is fully awake

and operational. After a PHY reset, or when returning from a

reduced power state, the PHY must be given adequate time to

return to the operational state before a soft reset can be issued.

The internal RX_CLK and TX_CLK signals must be running for a

proper software reset. Refer to Section 6.8 for details on PHY

reset timing.

Note:

The LAN89218 must always be read at least once after power-up,

reset, or upon return from a power-saving state or write operations

will not function.

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