LAN89218 datasheet(84/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 84

 2008-2015 Microchip Technology Inc.

RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate independent of the

TX data and RX data and status FIFOs. FIFO levels set for the RX and TX data and Status FIFOs do not take into

consideration the MIL FIFOs.

5.3.10

RX_DP_CTRL—RECEIVE DATAPATH CONTROL REGISTER

This register is used to discard unwanted receive frames.

5.3.11

RX_FIFO_INF—RECEIVE FIFO INFORMATION REGISTER

This register contains the used space in the receive FIFOs of the LAN89218 Ethernet Controller.

Offset:

78h

Size:

32 bits

Bits

Description

Type

Default

RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes the

RX data FIFO to fast-forward to the start of the next frame. This bit will remain

high until the RX data FIFO fast-forward operation has completed. No reads

should be issued to the RX data FIFO while this bit is high.

Note:

Refer to Section 3.13.1.1 for detailed information regarding the

use of RX_FFWD.

R/W

30:0

Reserved

Offset:

7Ch

Size:

32 bits

Bits

Description

Type

Default

31:24

Reserved

23:16

RX Status FIFO Used Space (RXSUSED). Indicates the amount of space in

DWORDs, used in the RX Status FIFO.

00h

15:0

RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in

bytes, used in the RX data FIFO. For each receive frame, this field is incre-

mented by the length of the receive data rounded up to the nearest DWORD

(if the payload does not end on a DWORD boundary).

0000h

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