LAN89218 datasheet(44/148 Pages) MICROCHIP

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LAN89218

DS60001255B-page 44

 2008-2015 Microchip Technology Inc.

3.11.2

HARDWARE RESET INPUT (NRESET)

A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the PMT_CTRL register

can be read from the host interface, and will read back a ‘0’ until the hardware reset is complete. Upon completion

of the hardware reset, the READY bit in PMT_CTRL is set high.

After the “READY” bit is set, the LAN89218 can be configured via its control registers. The nRESET signal is pulled-

high internally by the LAN89218 and can be left unconnected if unused. If used, nRESET must be driven low for a

minimum period as defined in Section 6.8.

3.11.3

SOFT RESET (SRST)

Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will return to ‘0’

after approximately 2 µs, at which time the Soft Reset is complete. Soft reset does not clear control register bits

marked as NASR.

3.11.4

PHY RESET TIMING

The following sections specify the operation and time required for the internal PHY to become operational after

various resets or when returning from the reduced power state.

3.11.4.1

PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)

The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This self-clearing bit

will return to ‘0’ after approximately 100 µs, at which time the PHY reset is complete.

3.11.4.2

PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)

The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-

clearing bit will return to ‘0’ at which time the PHY reset is complete.

3.12

TX Data Path Operation

Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may be divided

among multiple buffers. Each buffer starts with a two DWORD TX command (TX command ‘A’ and TX command ‘B’).

The TX command instructs the LAN89218 on the handling of the associated buffer. Packet boundaries are delineated

using control bits within the TX command.

The host provides a 16-bit Packet Tag field in the TX command. The Packet Tag value is appended to the

corresponding TX status DWORD. All Packet Tag fields must have the same value for all buffers in a given packet.

If tags differ between buffers in the same packet the TXE error will be asserted. Any value may be chosen for a

Packet Tag as long as all tags in the same Packet are identical. Packet Tags also provide a method of

synchronization between transmitted packets and their associated status. Software can use unique Packet Tags to

assist with validating matching status completions.

A Packet Length field in the TX command specifies the number of bytes in the associated packet. All Packet Length

fields must have the same value for all buffers in a given packet. Hardware compares the Packet Length field and

the actual amount of data received by the Ethernet controller. If the actual packet length count does not match the

Packet Length field as defined in the TX command, the Transmitter Error (TXE) flag is asserted.

Note:

For proper operation in applications where brown-outs may occur, use of an external reset circuit is recom-

mended.

Note:

Following deassertion of a hardware reset, the READY bit in PMT_CTRL will be set (high -”1”) immediately.

If the software driver polls this bit and it is not set within 100 ms, then an error condition occurred.

Note:

Following deassertion of a soft reset, the READY bit in PMT_CTRL will be set (high -”1”) within 2 µs. If the

software driver polls this bit and it is not set within 100 ms, then an error condition occurred.

Note:

The use of packet tags is not required by the hardware. This is a software LAN driver only application exam-

ple for use of this field.

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