Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

AD6684 Datasheet(PDF) 79 Page - Analog Devices

Part # AD6684
Description  135 MHz Quad IF Receiver
PDF  107 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD6684 Datasheet(HTML) 79 Page - Analog Devices

Back Button AD6684 Datasheet HTML 75Page - Analog Devices AD6684 Datasheet HTML 76Page - Analog Devices AD6684 Datasheet HTML 77Page - Analog Devices AD6684 Datasheet HTML 78Page - Analog Devices AD6684 Datasheet HTML 79Page - Analog Devices AD6684 Datasheet HTML 80Page - Analog Devices AD6684 Datasheet HTML 81Page - Analog Devices AD6684 Datasheet HTML 82Page - Analog Devices AD6684 Datasheet HTML 83Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 79 / 107 page
background image
Data Sheet
AD6684
Rev. 0 | Page 79 of 107
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0555
Pair Map
User
Pattern 3 LSB
User Pattern 3[7:0]
0x00
R/W
0x0556
Pair Map
User Pattern
3 MSB
User Pattern 3[15:8]
0x00
R/W
0x0557
Pair Map
User
Pattern 4 LSB
User Pattern 4[7:0]
0x00
R/W
0x0558
Pair Map
User
Pattern 4
MSB
User Pattern 4[15:8]
0x00
R/W
0x0559
Pair Map
Output
Control
Mode 0
Reserved
Converter control Bit 1 selection
Reserved
Converter control Bit 0 selection
0x00
R/W
0x055A Pair Map
Output
Control
Mode 1
Reserved
Converter control Bit 2 selection
0x01
R/W
0x0561
Pair map
output
sample
mode
Reserved
Sample invert
Data format select
0x01
R/W
0x0564
Pair map
output
channel
select
Reserved
Reserved
Con-
verter
channel
swap
control
0x00
R/W
0x056E
JESD204B
map PLL
control
JESD204B lane rate control
Reserved
0x00
R/W
0x056F
JESD204B
map PLL
status
PLL lock
status
Reserved
0x00
R
0x0570
JESD204B
map JTX
quick
configuration
Quick Configuration L
Quick Configuration M
Quick Configuration F
0x49
R/W
0x0571
JESD204B
map JTX Link
Control 1
Standby
mode
Tail bit
(t) PN
Long
transport
layer test
Lane synchronization
ILAS sequence mode
FACI
Link
control
0x14
R/W
0x0572
JESD204B
map JTX Link
Control 2
SYNCINB±AB/
SYNCINB±CD pin
control
SYNC-
INB±AB/
SYNCINB±CD
pin invert
SYNCINB±AB/
SYNCINB±CD pin type
Reserved
8-bit/10-bit
bypass
8-bit/10-bit
invert
Reserved 0x00
R/W
0x0573
JESD204B
map JTX Link
Control 3
Checksum mode
Test injection point
JESD204B test mode patterns
0x00
R/W
0x0574
JESD204B
map JTX Link
Control 4
ILAS delay
Reserved
Link layer test mode
0x00
R/W
0x0578
JESD204B
map JTX
LMFC offset
Reserved
LMFC phase offset value
0x00
R/W
0x0580
JESD204B
map JTX DID
configuration
JESD204B Tx serial device identification (DID) value
0x00
R/W
0x0581
JESD204B
map JTX BID
configuration
Reserved
JESD204B Tx serial bank identification (BID) value
0x00
R/W
0x0583
JESD204B
map JTX
LID 0
configuration
Reserved
Lane 0 serial lane identification (LID) value
0x00
R/W



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com